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Processor to Processor Communication with Nonmandatory Response

IP.com Disclosure Number: IPCOM000081686D
Original Publication Date: 1974-Jul-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Lang, DJ: AUTHOR [+3]

Abstract

In systems consisting of two or more sets of multiple processors each of which is capable of executing identical tasks, a problem arises in signaling from one set to the other that a task or multiple tasks are awaiting service in a common queue residing in a shared memory. In previous schemes, a processor from the first set would distribute a pulse to all the processors in the second set indicating that a new task had been added to the queue. Each processor in the second would retain (latch-up) the signal until it was prepared to respond; i.e., all prior tasks were completed.

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Processor to Processor Communication with Nonmandatory Response

In systems consisting of two or more sets of multiple processors each of which is capable of executing identical tasks, a problem arises in signaling from one set to the other that a task or multiple tasks are awaiting service in a common queue residing in a shared memory. In previous schemes, a processor from the first set would distribute a pulse to all the processors in the second set indicating that a new task had been added to the queue. Each processor in the second would retain (latch-up) the signal until it was prepared to respond; i.e., all prior tasks were completed.

Eventually one of the processors of the second set will invoke the execution of a routine which will access the queue, lock it to prevent further access and modification and remove a task for execution; further, since the depth of the queue is unknown, that processor must complete all enqueued tasks before releasing (unlocking) the queue. Meanwhile, the remaining second set processors must attempt to access the queue (only to find it locked) even though only one entry may have been enqueued.

Frequently the processors of all sets continue to acquire control of the queue until they find it unlocked. It is during this time that the processors waste performance and unnecessarily cause memory references.

An alternative scheme for the first set processor to signal the second set processors of work tasks, consists of a simplex communication network connecting each first set processor with each second set processor. Only one of the second set processors is signaled at a time. While his method solves the unnecessary memory access problem, its cost is considerable and the first set processors must have greater intelligence and knowledge of the second set processor's activities; more shared storage is utilized to maintain separate task queues; and more cabling is required thus increasing error frequency. In essence the second set processors become slaves to the first set processors. Consequently such a scheme often results in one second set processor being overloaded, while the others within the set remain relatively idle.

Herein is described a method which optimizes the efficiency of the cross signaling between two sets of processors. It allows only those second set processors capable of responding to service the signal from the first set processor. The remaining second set processors (those which were busy when the signal was distributed) are not obligated to respond. When the busy processors have completed their current tasks, only then are they obligated to service the signal if it is still active (i.e., queue was emptied by other second set processors and the signal was reset).

The system configuration is shown. The first set processors are shown as processing units A, PUA's; the second set as the processing units B, PUB's. The intervening level of control uni...