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Zero Modulation Look Ahead Using First In/First Out Memory

IP.com Disclosure Number: IPCOM000081688D
Original Publication Date: 1974-Jul-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Ouchi, NK: AUTHOR

Abstract

An encoding algorithm for a zero modulation data code employs look-ahead information when encoding certain data=bits. The parity of the number of "1" data bits in a sequence must be known to encode each one data bit in the sequence. By inserting additional bits into the data, the look-ahead is limited to some fixed number of bits, N. The sides of the shift register used for storing the N bits increases linearly with N, the fixed number of bits. The look-ahead logic used in conjunction with the shift register increases as N/2/.

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Zero Modulation Look Ahead Using First In/First Out Memory

An encoding algorithm for a zero modulation data code employs look-ahead information when encoding certain data=bits. The parity of the number of "1" data bits in a sequence must be known to encode each one data bit in the sequence. By inserting additional bits into the data, the look-ahead is limited to some fixed number of bits, N. The sides of the shift register used for storing the N bits increases linearly with N, the fixed number of bits. The look-ahead logic used in conjunction with the shift register increases as N/2/.

A two-step look-ahead mechanism employs a first-in/first-out memory. The N bit look-ahead is divided into smaller units of W bits called words. The look- ahead for "1" string parity (SP) is computed on a word basis. The first step computes an effective SP bit for each word, and stores them in a first-in/first-out memory, which is N/W bits long. The second step performs the look-ahead for zero modulation encoding on a W+l bit basis, where the SP bit is chained to the low-order end of the data word. The W data bits are encoded and the SP bit is discarded.= The following word and its associated SP bit are then processed. This continues until all the N bits are encoded.

The 128-bit look-ahead is divided into l6 eight-bit words. A first-in/first-out memory 6a with a 16-bit capacity. At the end of the SP generation step, the SP bits are in memory 6a in SP(0), SP(1),.....SP(15) order. AND/OR circuit 3
determines the parity of the 1-string starting in the high-order bit of the word in gated register 2. AND circuit 5 gates the output of circuit 3 into memory 6a. For SP(15), the output of gate 5 is forced to "0". A bit is entered into 6a by activation of the shift control. A high-rate clock that is 16 times the word rate (twice the bit rate) is provided. AND circuit 7 gat...