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High Speed Parity Predictor for Adder

IP.com Disclosure Number: IPCOM000081691D
Original Publication Date: 1974-Jul-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Related People

Kuckein, PA: AUTHOR

Abstract

The circuit shown provides a high-speed means of parity prediction which is simpler and faster than the method shown in the prior art

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High Speed Parity Predictor for Adder

The circuit shown provides a high-speed means of parity prediction which is simpler and faster than the method shown in the prior art

The parity of the arithmetic sum of two binary numbers, P(S). can be calculated by P(S) = P(A) V P(B) V P(C) (1) or equivalently

P(S) = P(A)P(B)P(C)+P(A)P(B)P(C)+P(A)P(B)P(C)+P(A)P(B)P(C) (2). where P(A) and P(B) are the parities of the input numbers and P(C) is the parity of the carries within the operation. The problem is to generate the parity of the sum, P(S), at or before the time the sum itself is generated. In a carry look-ahead adder, which represents the fastest class of adders, the carry from the n-th stage, C(n), which is used in generating the sum bit for the (n + 1)th stage is generated by the function

C(n)=G(n)+T(n)G(n-1)+T(n)T(n-1)G(n-2)+T(n)T(n-1)T(n-2)G(n-3)+...(3) where

G(n) = A(n) B(n) (4) and

T(n) = A(n) + B(n) (5). with A(n) and B(n) representing the n-th bits of the inputs A and B, respectively. The reference then shows that the parity of the carries for a 4-bit adder group can be generated as

(Image Omitted)

where C(in) is the carry into the group and

H(n) is the half-sum defined as H(n) = A(n) V B(n) (7) or equivalently,

H(n) = T(n) V G(n) (8) the latter method giving better error-detect capabilities. Due to the dependency of the generation of P(C) on H(n) and the relative complexity of the equation, a hardware implementation of this equation is either cumbersome in terms of the number of circuits, or slow. Prior art implementation typically had 6 levels of delay or with considerable added complexity a minimum of 3 levels of delay.

The implementation described herein represents a faster, less complex circuit not dependent on H(n), which itself is generated with some delay after G(n) and T(n) if maximum error checking is sought. The parit...