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Common Mode Loading Circuit for Balanced Line System

IP.com Disclosure Number: IPCOM000081696D
Original Publication Date: 1974-Jul-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 65K

Publishing Venue

IBM

Related People

Taub, DM: AUTHOR

Abstract

When digital signals have to be transmitted in regions subject to interference, it is preferable to use a balanced transmission line. However difficulties still arise in detection of signals if substantial common-mode voltages occur on the line. This problem is minimized, as shown in Fig. 1, by connecting a balance between the line and the differential amplifier which operates as a signal detector, and connecting between the amplifier terminals and ground a circuit which behaves substantially like a resistance to common-mode voltages, but like an open circuit to differential-mode voltages.

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Common Mode Loading Circuit for Balanced Line System

When digital signals have to be transmitted in regions subject to interference, it is preferable to use a balanced transmission line. However difficulties still arise in detection of signals if substantial common-mode voltages occur on the line. This problem is minimized, as shown in Fig. 1, by connecting a balance between the line and the differential amplifier which operates as a signal detector, and connecting between the amplifier terminals and ground a circuit which behaves substantially like a resistance to common-mode voltages, but like an open circuit to differential-mode voltages.

Referring to Fig. 2 this is accomplished by sensing the value of the common- mode voltage v(c) at terminals P and Q, and applying to both P and Q equal currents whose polarity is such as to reduce v(c).

The task of sensing the common-mode voltage is carried out by section A. The steady current I(ref) through R1 and T1 is mirrored by T4 and T5, which draw equal currents from the common-collector stages T2 and T3.

Suppose the input at P and Q consist of a common-mode voltage v(c) relative to ground, and a differential-mode voltage v(d). Then the voltages at P and Q will be, respectively, v(p) = v(c) + 1/2 v(d)

v(q) = v(c) - 1/2 v(d).

To a good approximation, the output of the common-collector stages T2 and T3 can be represented as voltage generators whose values are, respectively, v(2) = v(c) + 1/2 v(d) - V(be)

v(3) = v(c) - 1/2 v(d) - V(be) where V(be...