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Full Adder With Only Two Josephson Tunneling Gates Per Stage

IP.com Disclosure Number: IPCOM000081700D
Original Publication Date: 1974-Jul-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Herrell, DJ: AUTHOR

Abstract

An improved full adder circuit is provided which requires only two Josephson tunneling gates per stage, where each gate is made to exhibit different switching thresholds by control of the width of the tunneling barrier.

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Full Adder With Only Two Josephson Tunneling Gates Per Stage

An improved full adder circuit is provided which requires only two Josephson tunneling gates per stage, where each gate is made to exhibit different switching thresholds by control of the width of the tunneling barrier.

Figs. 1 and 2 illustrate in block diagram form, alternate circuits with their corresponding plots of the switching characteristics of the carry gates C and sum gates S for each circuit. The switching characteristic is depicted as a plot of the gate current I(g) versus the control current input I(c). Different points along the I(c) axis of each plot are labelled in ascending order, denoting additive units of control current input.

Inputs to gates C and S are A(n), B(n) and C(n-1), while the output C(n) is for the carry gate C in Figs. 1 and 2 and output S(n) denotes the output for the sum gate S. The output of gate C is connected to the sum gate S as an input. A pulse bias I(b) is applied to the S gate in both Figs. 1 and 2, but differs in that in Fig. 1, the bias in terms of units of current is -2I, while in Fig. 2, it is +2I.

In Fig. 1, it may be seen that a single unit I of control current is normally required to switch gate S, while two units of control current 2I are required to switch gate C. The bias I(b) is clocked to be energized prior to the application of input signals and to terminate before their decay. Hence, upon energization of one of the input lines A(n), B(n) or C(n-1), the gate C remains OFF and upon terminat...