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Nonlatching Loop Circuit in Josephson Tunneling Techniques

IP.com Disclosure Number: IPCOM000081702D
Original Publication Date: 1974-Jul-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Matisoo, J: AUTHOR

Abstract

A circuit arrangement in which output always follows input, requiring no reset of the current supply can be achieved for superconductive loops containing two Josephson tunneling devices, by insuring that the application of a control pulse switches the driving gate while at the same time raising the threshold of the other gate (these gates being connected in parallel, supplied from a common source). This second gate in the absence of the control pulse and carrying the gate current, is in the voltage state. This insures that when the control signal to the first gate is removed, the second gate switches to drive the gate current back. The circuit is then ready for the next operation without need to reduce the gate current level.

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Nonlatching Loop Circuit in Josephson Tunneling Techniques

A circuit arrangement in which output always follows input, requiring no reset of the current supply can be achieved for superconductive loops containing two Josephson tunneling devices, by insuring that the application of a control pulse switches the driving gate while at the same time raising the threshold of the other gate (these gates being connected in parallel, supplied from a common source). This second gate in the absence of the control pulse and carrying the gate current, is in the voltage state. This insures that when the control signal to the first gate is removed, the second gate switches to drive the gate current back. The circuit is then ready for the next operation without need to reduce the gate current level.

Fig. 1 schematically illustrates the principle. The details are intended to be illustrative only. The gain curves are chosen to be, for example, as shown in Fig.
2.

I(g) is chosen so that if I(c) = 0, I(m(a)) (0) > I(g) and I(m(b)) (0) < I(g). When I(c) > 0, its value is chosen so that I(m(a)) (I(c)) < I(g) and I(m(b)) (-I(c)) > I(g) as indicated by point 1 in Fig. 2. The I(c) polarity is wired in as in Fig. 1. The operation of the circuit then follows.

With I(c) = 0, all I(g) flows in gate a. Note in Fig. 2 that point 1 is within the gain curve for gate a, but without the gain curve for gate b. Under these circumstances, gate a is superconducting while gate b is in the sensitive state. Applying I(c) switches a to point...