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Timing Generator with Coarse and Fine Tuning

IP.com Disclosure Number: IPCOM000081744D
Original Publication Date: 1974-Jul-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Annunziata, EJ: AUTHOR [+3]

Abstract

This circuit using array logic 10 provides a timing generator with coarse and fine tuning.

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Timing Generator with Coarse and Fine Tuning

This circuit using array logic 10 provides a timing generator with coarse and fine tuning.

A string of bits are located in the array logic circuit 10, so as to produce a string of pulses when the array logic circuit is sequenced through all its positions of the system clock. The leading edge of the timing pulse starts when the first bit of the string of pulses is read out of the array. Each subsequent bit in the string causes the length of the timing pulse to be extended. The number of bits in the string being selected to give the desired length of the timing pulse.

Fine tuning for this circuit is provided by two latch/trigger circuits 12 and 14 that feed one ACT circuit 16 providing the output for the circuit. The latches receive the output of the array 10 along with a pulse from a fixed delay crosspoint switch 18. The accuracy with which the leading and trailing edges can be selected are a function of the skewed oscillator pulses that are supplied to the input of the crosspoint switch 18. This article replaces the publication appearing in the IBM Technical Disclosure Bulletin of May 1974, Vol. 16 No. 12 pages 4001 and 4002.

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