Browse Prior Art Database

Semiconductor Chip or Wafer Stacking Technique

IP.com Disclosure Number: IPCOM000081754D
Original Publication Date: 1974-Aug-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Audi, RD: AUTHOR [+2]

Abstract

In semiconductor chip or wafer packaging wherein it is desirous to stack the chips or wafers on substrates, utilizing conventional pins and solder bucket techniques, a tool comprising a body member 1 and a multiplicity of recessed and tapered holes 2 is provided. The tool 1 can be formed of any suitable material such as metal or plastic. Solder rings 3 are placed upon the surface of the tool and vibrated into the recessed segment of each hole 2.

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Semiconductor Chip or Wafer Stacking Technique

In semiconductor chip or wafer packaging wherein it is desirous to stack the chips or wafers on substrates, utilizing conventional pins and solder bucket techniques, a tool comprising a body member 1 and a multiplicity of recessed and tapered holes 2 is provided. The tool 1 can be formed of any suitable material such as metal or plastic. Solder rings 3 are placed upon the surface of the tool and vibrated into the recessed segment of each hole 2.

A semiconductor chip or wafer carrier 4 having a multiplicity of pins 5 is inserted into the tool 1 and inverted as shown in Fig. 3, so that solder rings 3 fall around pins 5, whereupon the tool is removed. The bucket side of semiconductor chips or wafers 6 are placed upon the pins 5 and inverted, as shown in Fig. 4, so as to allow the solder rings 3 to fall upon the bucket and in a position for reflow.

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