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Low Cost Communications Network

IP.com Disclosure Number: IPCOM000081790D
Original Publication Date: 1974-Aug-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 8 page(s) / 240K

Publishing Venue

IBM

Related People

Dennison, JD: AUTHOR [+4]

Abstract

A communications network is configured in either star or loop form where each transceiver is capable of assuming control. Self-clocking codes are used and thus eliminate phase locking and precision clocks. Optically coupled communication lines are driven by a current source. A transceiver can be in an idle, transmit or receive mode. All transceivers remain in the idle mode until device action or loop action force a transceiver out of that mode.

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Low Cost Communications Network

A communications network is configured in either star or loop form where each transceiver is capable of assuming control. Self-clocking codes are used and thus eliminate phase locking and precision clocks. Optically coupled communication lines are driven by a current source. A transceiver can be in an idle, transmit or receive mode. All transceivers remain in the idle mode until device action or loop action force a transceiver out of that mode.

A multidrop configuration is shown in Fig. 1 and a star configuration with a central control unit is represented in Fig. 2. Communication is carried out using a ten-bit byte. The high-order eight bits are the information field and the remaining two bits form an identifier (ID), see Fig. 3. Thus, a byte may be an address, data, error or end byte.

Each transceiver consists of a transmitter 20, Fig. 4, a receiver 40, Fig. 5, a controller 70, Fig. 6, byte comparator logic 100, Fig. 7, and driver-receiver logic 130, Fig. 8.

A normal communications sequence begins with a device raising the transmit request line (XR) to controller 70 of the transceiver. The transceiver is continuously monitoring the network to determine its availability. The loop appears unavailable until the transceiver receives two consecutive end codes. A first end code allows the transceiver to sink the loop. This action blocks bytes from being passed onto the next transceiver.

If the second end code is received, the transceiver takes the device address present on the address bus and transmits that byte out on the loop. This address byte serves to notify other devices on the loop that a particular device wants control of the loop. If other devices on the loop are seeking loop control, they will drop their sink status and re-transmit the address message on the receipt of the address byte. This address message also informs the transceiver which previously had control of the loop that control may now be transferred.

During the operation of the loop, it becomes busy between the time when one device gains control of the loop and when that same device begins sending the end ID coded bytes on the loop. As end codes are received by the transceiver which is connected to the device wishing to transmit, these end codes are counted. The first end code is gated by AND circuit 71, Fig. 6, to ring counter 72. The first position of ring counter 72 is connected to inverter 73 and its output is the sink line. When a second end code is received from the loop, the transceiver goes into the transmission mode and clocks on line 74 are gated via AND circuit 75 into ring counter 76. AND circuit 75 is conditioned at this time via AND circuit 77 and OR circuit 78 and by AND circuit 79.

The first pulse sent out on the line is a time out generator bit TOG. This TOG bit is passed from ring counter 76 via AND circuit 80. As the count continues through ring counter 76 and it completely cycles, clocks are sent to the attached ...