Browse Prior Art Database

Nondestructive Readout Memory

IP.com Disclosure Number: IPCOM000081825D
Original Publication Date: 1974-Aug-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Kalter, HL: AUTHOR

Abstract

This memory cell includes a diode 10, a capacitor 12 into which information is written and a field effect transistor 14 through which the information is read out, as shown in Fig. 1.

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Nondestructive Readout Memory

This memory cell includes a diode 10, a capacitor 12 into which information is written and a field effect transistor 14 through which the information is read out, as shown in Fig. 1.

During a write operation, if a "1" is to be stored, the word line is pulsed to -10 volts and the bit line is pulsed to +10 volts to apply a voltage of -5 volts at the gate of transistor 14. If a "0" is to be stored, the word line is pulsed to +10 volts and the bit line is pulsed to zero volts to provide a zero bias at the gate of transistor 14.

In the read operation, the word line and the bit line are pulsed to +10 volts causing the voltage at the gate of transistor 14 to increase only to a voltage below the threshold voltage of transistor 14, if a "0" has been stored, so that current does not flow to the sense line. If a "1" has been stored, the voltage at the gate of transistor 14 rises above its threshold voltage and current flows through transistor 14 into the sense line.

During the write operation, diode 10 may be forward biased or reverse biased to breakdown to store a charge on capacitor 12 when storing a "0" or a "1", respectively. Current flows during the write operation only when charging or discharging capacitor 12. A more complete pulse program for operating the cell of Fig. 1 is indicated in Fig. 2. It should be noted that the voltage values indicated at point A or at the gate of transistor 14 are due, in part, to the presence of voltage-var...