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Associative Memory Sense Signal Scheme

IP.com Disclosure Number: IPCOM000081826D
Original Publication Date: 1974-Aug-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Kemerer, DW: AUTHOR

Abstract

This scheme utilizes conventional MOSFET memory cells in an associative memory array which are sensed in a single-ended voltage signal arrangement.

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Associative Memory Sense Signal Scheme

This scheme utilizes conventional MOSFET memory cells in an associative memory array which are sensed in a single-ended voltage signal arrangement.

In an associative memory array, many word lines are addressed simultaneously. When all word lines "match" the cell nodes, sense current does not flow in bit line BLO and BLO is held at the potential VLL. When a word line "mismatches" the corresponding cell node, current flows in BLO and a voltage drop is detected in the sense signal detection circuit. If more than one Word line "mismatches" the cell nodes, it is desirable, in the interest of retaining information in the memory cells, to have no additional voltage drop across transistor T10. Because resistors R01 and R02 and transistor T14 hold voltage VLT at a value equal to voltage VLL plus one threshold voltage, the square-law current characteristic of transistors T10 and T12 ensures that the voltage on B:LO and D:LO only drops a voltage proportional to the square root of the number of cells drawing current on each line, the current characteristic Id being gamma W over L(V(G)-V(S)-V(T))/2/, where V(G), V(S) and V(T) are the gate, source and threshold voltages, respectively, and W and L are the width and length, respectively, of the transistors T10 and T12.

Transistors T16 and T18 provide a reference level VRL for the detection circuit equal to one half the voltage drop caused by the current flowing through a single cell. Transi...