Browse Prior Art Database

Refresh Circuit

IP.com Disclosure Number: IPCOM000081827D
Original Publication Date: 1974-Aug-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Gray, KS: AUTHOR [+2]

Abstract

This circuit stores data and controls word lines in a memory array which is particularly suitable for associative memory applications.

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Refresh Circuit

This circuit stores data and controls word lines in a memory array which is particularly suitable for associative memory applications.

The circuit includes a four-device storage latch 10 having field effect transistors 12, 14, 16 and 18, as shown in Fig. 1. An invert and latch refresh circuit 20 includes a six-device storage latch having field effect transistors 22, 24, 26, 28, 30 and 32 and a pair of field effect transistors 34 and 36, which provide an alternate coupling path between four-device latch 10 and the six-device storage latch. A pulse program for operating the circuit of Fig. 1 is indicated in Fig. 2.

In operation, external data is loaded into latch 10 by applying true and complement input data through transistors 16 and 18 and simultaneously raising clock 2 and load pulse, as indicated in Fig. 2. To perform the invert and refresh operation, clock 2 and load pulse are lowered to store in circuit 20 the information stored in latch 10. When clock 1 is raised and then lowered, the information in latch 10 is inverted. Since word line 1 is controlled by node A and word line 2 is controlled by node B, one of the word lines 1 and 2 is selected during the external data loading and the other word line is selected during the inverting portion of the pulse program cycle, depending upon the data stored in latch 10. During word line selection operations, the information is destroyed in latch circuit 20 by raising clock 2 to prepare circuit 20 for i...