Browse Prior Art Database

Address Encoding Circuit

IP.com Disclosure Number: IPCOM000081828D
Original Publication Date: 1974-Aug-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Anderson, KL: AUTHOR

Abstract

This circuit provides a high performance, low power address encoder with select signal-load isolation. The encoder allows the decoding circuitry to receive signals quickly and to perform decoding functions rapidly.

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Address Encoding Circuit

This circuit provides a high performance, low power address encoder with select signal-load isolation. The encoder allows the decoding circuitry to receive signals quickly and to perform decoding functions rapidly.

Main memory arrays require the use of signals from storage address registers to locate data in storage. This circuit generates inverted and buffered SAR signals for use in locating this stored data. In this circuit the address signals (SAR) are isolated from the chip-selection signal (CS).

Signal R is a chip-restoring signal which charges the gates of field effect transistors (FETs) 4 and 13 through FETs 1 and 8, respectively. Also, the signal R charges the drain of FET 12 through device 11. In addition to charging these points, signal R also discharges any signal that may be on the inverted or buffered signal lines SARinvert and SARbuffer. After applying signal R, the circuit is prepared for the arrival of the input address SAR.

If SAR is at ground, FET 2 remains OFF and node A remains charged. However, FET 9 is ON and conducting until node C is charged via FETs 8, 9 and
11. When. signal CS appears, signal R goes to ground, and nodes B and C are discharged via FETs 9 and 12. This prevents FET 13 from conducting and charging the gate of FET 15, thus preventing the SARbuffer from rising. SARbuffer is then a true indication of input address SAR. With CS up and the gate of FET 4 preconditioned, FET 4 conducts and charges the gate...