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Serial Processing of Interleaved Codes

IP.com Disclosure Number: IPCOM000081834D
Original Publication Date: 1974-Aug-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Bossen, DC: AUTHOR [+2]

Abstract

By interleaving N copies of a basic b-adjacent and subfield code, a code word can be constructed to correct any arbitrary bits of (N-1) b + 1 bits in error in a single track of a disk or tape system.

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Serial Processing of Interleaved Codes

By interleaving N copies of a basic b-adjacent and subfield code, a code word can be constructed to correct any arbitrary bits of (N-1) b + 1 bits in error in a single track of a disk or tape system.

Consider a segment length of 1116 bits which consists of three interleaved codes with symbols from GF (2/6/). The code is described by the parity check matrix shown below.

(Image Omitted)

where T/63/ = I. Both T and I matrices are 6 x 6 square matrices.

The redundancy for this code is 2/62 = 3.1%. The error correction capability per segment is: (i) one long burst of length < or = 13 bits (ii) three non- overlapped short bursts of length < or = 6. We denote the fact of three-way interleaving by referring to the three codes as A, B and C. The encoder for this code consists of an 18-stage shift register, a 12-stage shift register, as shown in the figures, and two 6-stage shift register buffers. At the end of the data entering the shift registers, the check bits can be serially fed out onto the media.

In general, the serial implementation requires the control of a b-bit counter. For this particular example, a 6-bit counter is used to control multiplication of the contents of SR2 by T and storage of the result in SR3. This occurs after every 6th bit of data. The control signal G(c) derived from the 6-bit counter is shown relative to the data clock.

As the data is read from the media, the encoder receives the data and check bits in th...