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Array Logic With Dynamic Bit Selection and 4 State Crosspoint Conditioning

IP.com Disclosure Number: IPCOM000081835D
Original Publication Date: 1974-Aug-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Jones, JW: AUTHOR [+2]

Abstract

Packaging and utilization of array-structured associative logic is enhanced by providing dynamic selection control on inputs (bit lines) and 4-state crosspoint switching of complementary (phase-split) inputs. This allows the switching personality needed for relatively exclusive logical translation functions to be concentrated into smaller bit-word sub-arrays.

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Array Logic With Dynamic Bit Selection and 4 State Crosspoint Conditioning

Packaging and utilization of array-structured associative logic is enhanced by providing dynamic selection control on inputs (bit lines) and 4-state crosspoint switching of complementary (phase-split) inputs. This allows the switching personality needed for relatively exclusive logical translation functions to be concentrated into smaller bit-word sub-arrays.

Fig. 1 shows this for an intersection cell associated with one pair of complementary inputs (A, A) and a crossing (word line) of an AND array. Bistable connecting elements L and R are set in combination to one of four possible states (00, 01, 10, 11). The word-line output is inverted and coupled to selected output lines in the OR array. The inputs A and A are "gated" separately or concurrently by respective Select 1 and Select 0 controls. The below shows the resulting state relationships.

(Image Omitted)

Fig. 2 shows how this cell configuration can be used in a 40 point AND sub- array of eight inputs by five word lines to selectively increment and decrement a 4-bit input argument. The "T" connections to the OR array have "toggles" which are switched when a "match" indication occurs on the associated word line. Thus, the top word line of all 00 (Don't Care) cells complements the associated toggle in each cycle of array operation providing a "least significant digit" output alternating cyclically between 0 and 1.

Due to the feedback con...