Browse Prior Art Database

Encoder Resolver Array for Content Addressable Memory

IP.com Disclosure Number: IPCOM000081863D
Original Publication Date: 1974-Aug-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 4 page(s) / 88K

Publishing Venue

IBM

Related People

Davidson, EE: AUTHOR

Abstract

The Encoder/Resolver array of Fig. 1 is used for setting out priorities and identifying multiple match addresses during a Content Addressable Memory (CAM) search operation. Propagation delay and total array loading are minimized.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 41% of the total text.

Page 1 of 4

Encoder Resolver Array for Content Addressable Memory

The Encoder/Resolver array of Fig. 1 is used for setting out priorities and identifying multiple match addresses during a Content Addressable Memory (CAM) search operation. Propagation delay and total array loading are minimized.

Any number of match lines in Fig. 1 can present a signal to the Encoder/Resolver array. There will be a signal for each CAM word that agrees with the masked search information. Initially, the Encoder/ Resolver output circuitry indicates whether no match, a single match or a multiple match has occurred.

For the case in which no match has occurred, the system is instructed to ignore any Match Address output. For a single match situation, the address of the matched word is presented at the Match Address port. In the multiple-match case, the Encoder/Resolver sets out the priorities for the matches such that the highest-order binary address is encoded as the match address. Remaining matches in the multiple-match case can be ferreted out by manipulation of the search-tag bit during successive search cycles that reoccur until all of the matches are exhausted.

In the example of Fig. 1, there are 32 input match lines and five encoded output column lines. The sixth column line is used for detecting the single and multiple match conditions. Operation of the match detection line 1 involves a switchable voltage divider action. Device QA is effectively a resistor that charges the match detection line up to +V. When one of the match lines goes high, the output of the associated inverter goes low and turns one of devices Q 0' through Q 31' on. This lowers the voltage on the match detection line to some intermediate value V1. If two match lines go high, then two of the Q 0' through Q 31' transistors are turned on and the match detection line traverses to a voltage that is lower in magnitude than V1, i.e., V2. A greater plurality of active match lines than two causes the line voltage to go below V2.

In summary, any match detection line voltage that is higher in magnitude than V1 is a "no match", any line voltage between V1 and V2 is a single match and any line voltage less than V2 is a multiple match. Therefore, a Double Level Detector circuit is required that can discriminate between the V1 and V2 levels. Such a circuit is illustrated in Fig. 2.

When V1 on the match detection line is applied to the source terminal of Q1, Q1 turns on and causes the voltage at node A to fall sufficiently such that Q6 turns off and Q5 turns on. This causes the single match line to go high. For the case when the match detection line is higher than V1, Q1 is off and Q4 keeps Q6 on and Q5 off. Consequently, the single match output line is low. Q2 and Q3 form a voltage divider for setting the voltage reference for Q1 (VR1).

The circuit consisting of Q7-Q12 performs the same function for detecting V2 on the match detection line that the circuit consisting of Q1-Q6 performs for detecting V1. As...