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Double Direct Coupled Inverter Circuit Layout

IP.com Disclosure Number: IPCOM000081872D
Original Publication Date: 1974-Aug-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Eichelberger, EB: AUTHOR [+4]

Abstract

A standard AND-INVERT internal cell semiconductor structure of the TTL family can be used to construct a double direct-coupled inverter circuit. The design offers the advantage of increasing the functionality of the semiconductor chip because only one, instead of two, NAND cells is used for providing the two inverters. In addition, a cell can be used for providing a clamp function at twice the density of the standard design.

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Double Direct Coupled Inverter Circuit Layout

A standard AND-INVERT internal cell semiconductor structure of the TTL family can be used to construct a double direct-coupled inverter circuit. The design offers the advantage of increasing the functionality of the semiconductor chip because only one, instead of two, NAND cells is used for providing the two inverters. In addition, a cell can be used for providing a clamp function at twice the density of the standard design.

Fig. 1 shows the standard TTL cell diffusions. Four P-type resistors 4 and 4' are formed above N+ subcollector region 13. A P+ isolation region 6 separates the resistors from the active devices which are formed above subcollector 3 and epitaxial layer 7. The emitter regions are formed in a P-type region 8 which comprises the base of the devices. Regions 9 and 10 become Schottky barrier diode regions upon the deposition of appropriate metallization on the surface of the substrate.

The connection of the standard cell to form the inverter circuit is shown by the wiring diagram in Fig. 1 which is comparable to the circuit diagram of Fig. 2. The collector voltage of V(CC) is connected to a contact 11 which makes ohmic contact with resistor regions 4 and 4'. Output 24 of the inverter circuit is connected to the resistors 4 and collector c1. In a similar manner, output line 25 is connected to resistors 4' and collector c2. Emitters e1 and e2 are connected to the emitter voltage of V(EE). Input 21 is conn...