Browse Prior Art Database

Compressed Buffer Storage

IP.com Disclosure Number: IPCOM000081879D
Original Publication Date: 1974-Aug-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Berta, EJ: AUTHOR [+2]

Abstract

At the expense of a few control circuits, the modified shift register storage shown in the figure uses half the number of circuits as the conventional shift register which includes a master and slave circuit in each stage. At the completion of a load operation the modified shift register contains each byte of data in either a master latch or a slave latch, but not both as in the conventional register.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 56% of the total text.

Page 1 of 2

Compressed Buffer Storage

At the expense of a few control circuits, the modified shift register storage shown in the figure uses half the number of circuits as the conventional shift register which includes a master and slave circuit in each stage. At the completion of a load operation the modified shift register contains each byte of data in either a master latch or a slave latch, but not both as in the conventional register.

To the right in the figure, there is shown an 8-byte input buffer 10, each byte containing 8 bits. One byte at a time is shifted into the top position in the conventional manner, until the first byte reaches the bottom position. During this period of time logical "1's" are shifted into the tag register 12. As the first byte is shifted into the bottom position of input buffer 10, a logical 1 is shifted into the tag 8 position of the tag register 12. The tag register now contains all 1's.

Because the output of tag 8 is fed back to the input of tag 1 by feedback line 14, logical "0's" will now enter the tag register
12. On the next clock pulse, tag 1 goes to zero inhibiting any further shifting of data into the bottom position of the buffer 10.

At the next not clock time, tag 2 goes to zero. This prevents any further shifting of data into the second from the bottom position of the buffer register 10. This operation continues until all 8 bytes of data are locked into their proper position in the buffer register 10.

At this point, the tag regist...