Browse Prior Art Database

Simplified LSI Chip Data Input/Output Scheme

IP.com Disclosure Number: IPCOM000081881D
Original Publication Date: 1974-Aug-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Berta, EJ: AUTHOR [+2]

Abstract

Many LSI (Large Scale Integration) chip designs incorporate the storage of data on the chip. To minimize I/O pin requirements, data entry/exit is usually accomplished by shifting in/out a series of bytes of data. The requirement of shift registers for data storage, however, requires more logic than a system storing data in conventional registers.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 62% of the total text.

Page 1 of 2

Simplified LSI Chip Data Input/Output Scheme

Many LSI (Large Scale Integration) chip designs incorporate the storage of data on the chip. To minimize I/O pin requirements, data entry/exit is usually accomplished by shifting in/out a series of bytes of data. The requirement of shift registers for data storage, however, requires more logic than a system storing data in conventional registers.

Fig. 1 shows data entering a chip and rippling through a set of conventional registers 10. When sufficient time has elapsed for this data to settle down in the register 10, the gates 12 on the registers 10 are conditioned to trap the data. After this data is trapped, the gates 12 on all the preceding stages are opened allowing the next sequential data to enter and to ripple through the registers 10. Then the proper gate is reconditioned and the data is trapped in the adjacent preceding register. This process continues until all the registers are filled.

Each data register 10 is conditioned by a bit stored in a shift register 14, as shown in Fig. 1. Upon reset all 1's are put in the shift register 14. This conditions the data registers 10, allowing them to pass information through the entire string. When the first data byte has entered, a 0 is shifted into the low position of the shift register 14. This drops the gate 12 on the low-data register 10, trapping the data. Next, the input data changes to reflect the next byte. Again another 0 is shifted into the shift register 14. T...