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Low Power High Speed Level Shifter

IP.com Disclosure Number: IPCOM000081885D
Original Publication Date: 1974-Aug-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Wiedmann, SK: AUTHOR

Abstract

In logical circuit systems with different reference voltages, it is necessary for the logical levels with the higher reference voltage to be converted to the levels with the lower reference voltage.

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Low Power High Speed Level Shifter

In logical circuit systems with different reference voltages, it is necessary for the logical levels with the higher reference voltage to be converted to the levels with the lower reference voltage.

The circuit shown in the drawing is used for this purpose. The logical levels (VH and 0 volt) of the higher reference voltage VH are fed to the base of an (NPN) transistor T1 in common-emitter configuration. The collector output of T1 controls the base of a complementary (PNP) transistor T2 via a resistor R1. T2 serves as a current source for the base of an (NPN) transistor T3 in common- emitter configuration which is connected via a resistor R2. The logical levels (VN and VR), shifted in accordance with the lower reference voltage VN, are emitted on the collector output of T3. R1 and R2 serve to limit the base current of T2 and T3.

As the switching time of (PNP) transistor T2 is normally longer than that of (NPN) transistors T1 and T3, resistor R1, limiting the current available, is either chosen suitably low or replaced by a short circuit, in order to prevent a reduction in the switching speed of the level shifter. This measure ensures that the relatively high-time constant of T2 is compensated by the base-emitter diode of T2 being excessively saturated. After reaching the desired signal level at the collector of T2, the high-base current of the latter is reduced by a current control circuitry controlled by the collector signal of...