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Dynamic Building Block Logic Circuit With Feedback

IP.com Disclosure Number: IPCOM000081904D
Original Publication Date: 1974-Aug-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Williams, TA: AUTHOR

Abstract

Field-effect transistor (FET) logic circuits and associated dynamically controlled transfer gates may be appropriately combined to form building block logic circuits for metal-oxide semiconductor (MOS)FET functional macro elements.

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Dynamic Building Block Logic Circuit With Feedback

Field-effect transistor (FET) logic circuits and associated dynamically controlled transfer gates may be appropriately combined to form building block logic circuits for metal-oxide semiconductor (MOS)FET functional macro elements.

Fig. 1 shows an FET logic circuit 10, typically any combination of invert, NAND, NOR circuits and input transfer gates 12, 14 controlled by clock C1, and output transfer gate 16 controlled by clock C2. A feedback path 18 connects the output terminal D0 with an input terminal of transfer gate 14. C1 and C2 are nonoverlapping gate signals. A data signal at terminal D1 is inputted to the logic circuit 10 when clock C1 is raised. A prior data output signal is also provided as an input to the logic circuit 10. Clock C2 provides an output signal to the next logic stage, that output signal being provided as an input to gate 14 at C1 clock time.

Logic operation is completed only after both control signals C1 and C2 are processed.

Figs. 2 and 3 show the circuit of Fig. 1 arranged for operation as a counter. Logic gates 20 and 22 are placed between gate 16 and feedback path 18 to receive set (S) and reset (R) signals, respectively.

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