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High Speed Random Access Memory With Simultaneous Read Write Operation

IP.com Disclosure Number: IPCOM000081905D
Original Publication Date: 1974-Aug-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Williams, TA: AUTHOR

Abstract

High-speed memory operation may be obtained by partitioning a memory array and associated decode networks into parallel sections, so that read/write operations may be performed simultaneously.

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High Speed Random Access Memory With Simultaneous Read Write Operation

High-speed memory operation may be obtained by partitioning a memory array and associated decode networks into parallel sections, so that read/write operations may be performed simultaneously.

The figure shows a high-speed memory 10 fabricated in a semiconductor device by well-known processing steps. The memory 10 is divided into two or more portions "A" or "B". Each portion has an array portion 12, 12', decode 14, 14', write switches 16, 16', write drivers 18, 18', read switches 20, 20' and sense amplifiers/output latches 22, 22'. Memory portion A has separate decode, write 24 and read 26 control inputs. Memory B has similar inputs 24', 26' and decode inputs. The decode lines may be common to conserve terminal pads, not shown, and input/output pins, not shown, for the semiconductor device and supporting structure.

A write control signal at line 24 turns ON write switches 16 and drivers 18 for array 12. Input data D1...D15 is stored in the array 12 at the addresses provided to the decoder 14. Simultaneously, the sense amplifiers and output latches 22' are connected to the bit lines of array 12', allowing read out at the addresses indicated by decode section 14' after read switches 20' are turned ON. Read out of array 12 can be done during the next memory cycle while data D6...D30 is read in to array 12'.

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