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Fabricating Recessed Oxide Isolation Regions in Silicon Substrates

IP.com Disclosure Number: IPCOM000081914D
Original Publication Date: 1974-Aug-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 4 page(s) / 52K

Publishing Venue

IBM

Related People

Rideout, VL: AUTHOR [+2]

Abstract

An improved process which minimizes the width of the recessed oxide (ROX) region, thereby providing higher packing density of active devices, and which minimizes the spread of additional boron at the sides of the ROX region, thereby separating the boron channel stopper from the implanted or diffused regions of active devices at the silicon surface, is described. Minimizing the spread of the boron channel stopper, leads to better electrical isolation of active devices and reduced leakage from device to substrate for p-type silicon substrates.

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Fabricating Recessed Oxide Isolation Regions in Silicon Substrates

An improved process which minimizes the width of the recessed oxide (ROX) region, thereby providing higher packing density of active devices, and which minimizes the spread of additional boron at the sides of the ROX region, thereby separating the boron channel stopper from the implanted or diffused regions of active devices at the silicon surface, is described. Minimizing the spread of the boron channel stopper, leads to better electrical isolation of active devices and reduced leakage from device to substrate for p-type silicon substrates.

In a known process, an anisotropic etch was used to define a steep walled and flat bottomed hole or recess in (110) or (100) silicon. Subsequently, a thermal oxide (ROX) was grown in the recess. The advantage of the anisotropic etch over an isotropic etch is that the width of the ROX region is less, allowing higher packing density of active devices at the silicon surface. For p-type silicon substrates, boron was ion implanted after etching the recess to compensate for boron depletion which occurs during growth of the thermal oxide.

Using this prior art process, an SiO(2) layer approximately 4000 Angstroms thick was used as the implantation mask. A major problem associated with this thick SiO(2) implantation mask is that even though a very steep walled hole or recess can be opened in the resist using electron-beam techniques, excessive undercutting of the SiO(2) mask occurs during etching. The lateral undercutting is approximately equal to the SiO(2) thickness.

Furthermore, since the SiO(2) walls are sloped at an angle of approximately 45 degrees, the implantation masking capability is not 100% at the edges of the mask. This can produce an undesirably high-boron concentration on the side walls of the ROX region at the silicon surface. As a result, implanted or diffused source and drain regions of active devices immediately adjacent to the ROX region may exhibit reduced breakdown and/or excessive junction leakage.

If a photoresist layer is used as an ion implantation mask, rather than a thick SiO(2) layer, then a much thinner SiO(2) layer (e.g., less than 500 Angstroms) can be used, thereby relieving the SiO(2) undercutting problem discussed above. Fig. 1 shows a photoresist mask 1 having a thickness of 5000 Angstroms deposited on a layer 2 of SiO(2) having a thickness of 500 Angstroms and a layer 3 of Si(3)N(4) having a thickness of 500 Angstroms on a silicon substrate 4. The eventual mask opening 5 at the silicon surface will be 5000 Angstroms plus 500 Angstroms (for the SiO(2) mask) plus 500 Angstroms (for the Si(3)N(4)), or 6000 Angstroms total. Then the width of the ROX region will be 6000 Angstroms plus 80% x 4000 Angstroms (for the ROX undergrowth) or 9200 Angstroms total.

If an SiO(2) mask of 4000 Angstrom thickness is used, the mask opening at the silicon surface would be 5000 Angstroms plus 4000 Angstroms plus 500 Angst...