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Memory Board Address Interleaving

IP.com Disclosure Number: IPCOM000081940D
Original Publication Date: 1974-Sep-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Gifford, CE: AUTHOR [+3]

Abstract

A procedure is described which utilizes special memory board wiring and selective interchanging of cards on the board, to change a double-bit error (DBE) in one memory address to two single-bit errors (SBE) in two memory addresses. By the use of ECC (error correction circuits), the single errors can be corrected when the memory is accessed, whereas double-bit errors in a memory location were not correctable.

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Memory Board Address Interleaving

A procedure is described which utilizes special memory board wiring and selective interchanging of cards on the board, to change a double-bit error (DBE) in one memory address to two single-bit errors (SBE) in two memory addresses. By the use of ECC (error correction circuits), the single errors can be corrected when the memory is accessed, whereas double-bit errors in a memory location were not correctable.

A modified Hamming error correction code has the capability of detecting DBEs and correcting SBEs. The DBE is a hard machine malfunction which is typically corrected or recovered from, by operating the system at the expense of disabling the block of main store associated with the DBE, or by replacement of the malfunctioning card. SBEs are transparent to the system because they cause no system malfunction or interruption.

Significant savings of field maintenance personnel time and memory card cost can be achieved, if a malfunctioning card with one bit error (aligned with another SBE card in the same memory address) thereon can be interchanged with an error-free card to change one DBE to a pair of SBEs. This simple arrangement reduces the cost of correcting hard system failures, and at the same time provides the customers more continuous usage of all blocks of storage in their data processing systems.

A typical semiconductor memory consists of a plurality of interconnected memory boards such as board 1 of Fig. 1. A block of storage is physically located on a board. The board carries a plurality of array cards B-U inclusive, each of which includes four bit positions of each of a plurality of seventy-two bit double words.

A plurality of ceramic modules, such as module 3 (Fig. 2), are mounted on the card B. Each module carries a plurality of chips, such as chip 4 in Fig. 3, each chip being interconnected with input/output data lines, address lines and power supply lines. Each of the chips has a large plurality, e.g. 1024, of bit storing circuits, not shown.

Board 1 thus consists of a block of 32K words.

When a chip (i.e., 4) is addressed by a corresponding row and column line, such as...