Browse Prior Art Database

Current Driver for Inductive Loads with Pedestal

IP.com Disclosure Number: IPCOM000081951D
Original Publication Date: 1974-Sep-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Arnold, RW: AUTHOR

Abstract

The present circuit solves the problem of driving high currents into inductive loads, without dissipating high power in the output device. This is accomplished by reducing the voltage on the load when the desired current has been obtained, and resetting it to the higher level when the driver is again turned on. The data input is nonreturn to zero (NRZ).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Current Driver for Inductive Loads with Pedestal

The present circuit solves the problem of driving high currents into inductive loads, without dissipating high power in the output device. This is accomplished by reducing the voltage on the load when the desired current has been obtained, and resetting it to the higher level when the driver is again turned on. The data input is nonreturn to zero (NRZ).

The circuit schematic is shown in Fig. 1 and, for purposes of illustration, assume that the load is 50 mu h and the current desired is 1 amp. Under these conditions, it will take 3 m usec to get to 1 amp. The 1 amp current is produced by the data in. When the data is 1 volt, the current in transistors Q3 and Q4 is 1 amp. For comparison purposes, assume that transistors Q1 and Q2 are saturated and therefore the load is tied to the 24 volt supply. The slew rate of the operational amplifier 0A1 would be 0.33 volt/mu sec. This keeps transistor Q3 linear during turn on and away from breakdown during turn off. Typical waveforms are shown in Fig. 2. The power involved in transistor Q3 in this case is about 12 watts.

The circuit lowers the power in transistor Q3 by reducing the 24 volt supply to 6 volts after the current of 1 amp is reached. The waveforms are shown in Fig. 3. Assume that the data in and the load current waveforms of Fig. 2 still hold true. Initially assume that the data is 0 volts and the flip-flop FF is reset, whereby transistors Q1 and Q2 are on.

As the data becomes 1 volt, the single-shot SS is unaffected because it is negative edge triggered and the current starts rising to 1 amp. The collector of transistor Q3 come...