Browse Prior Art Database

Tunnel Transistor

IP.com Disclosure Number: IPCOM000081979D
Original Publication Date: 1974-Sep-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Miersch, E: AUTHOR

Abstract

The structure concerned is a metal-insulator semiconductor (MIS) structure, using extremely thin insulating layers that can be tunnelled through by charge carriers.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 64% of the total text.

Page 1 of 2

Tunnel Transistor

The structure concerned is a metal-insulator semiconductor (MIS) structure, using extremely thin insulating layers that can be tunnelled through by charge carriers.

From a lateral transistor structure, wherein two zones doped oppositely to the base zone and serving as emitter/collector are introduced into the base zone, the bipolar tunnel transistor of Fig. 1 essentially differs in that no correspondingly doped zones are provided for the collector and the emitter. The collector and emitter merely consist of a contact arranged on the base zone and which is separated from the base zone, by an extremely thin insulating layer that can be tunnelled through by charge carriers. This is not restricted to the lateral structure.

Fig. 1 shows a P- base zone 1 and an N- substrate 2 which, at least in the area of the collector and the emitter to be formed, is covered by insulating layer 3 that can be tunnelled through. Emitter contact 6 and collector contact 7 are disposed on this insulating layer 3 above polycrystalline silicon layers 4 and 5. The structure is completed by an N+ subcollector zone 8, lateral insulating regions 9 and a base contact 10.

Fig. 2 shows a corresponding field-effect transistor (FET) version. Similar to the bipolar version, source and drain are formed by an insulating layer 3 that can be tunnelled through, and on which polycrystalline silicon layers 4 and 5 and source and drain contacts 6 and 7 are arranged. The gate, consisting of...