Browse Prior Art Database

Single Ended Storage Mode Transistor Switching Circuit

IP.com Disclosure Number: IPCOM000081983D
Original Publication Date: 1974-Sep-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Hoffman, HS: AUTHOR

Abstract

This transistor switching circuit utilizes storage-mode principles, described heretofore in U. S. Patent 3 609,410, for example.

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Single Ended Storage Mode Transistor Switching Circuit

This transistor switching circuit utilizes storage-mode principles, described heretofore in U. S. Patent 3 609,410, for example.

Transistor Q turns on and drives a load through transformer X, and during Q off time transformer X recovers against the clamp. Q has its emitter connected to inductor L tap 10. One end 12 of L is connected to the base of Q, and its other end 14 is connected to the voltage supply return 16. The other bus 18 of the supply feeds a start-up pulse through resistors R1, R2 and capacitor C when voltage is first applied to 18.

To define a cycle of operation, consider Q to be coming on. Q receives regenerative drive from 10-12 and L is driven with load current through Q,-10, 14, until Q is in hard saturation. At this point, although L-saturates, Q remains on in storage. At the beginning of depletion in Q, and current fall, the voltage of L reverses, driving the stored charge out of Q rapidly.

The magnetizing current in L continues and begins to charge capacitor C through diode D; zener DZ clips the voltage. When the inductor current has died, C discharges through diode D backwards to build current up in L in the reverse direction. The voltage of C goes through zero and rises until its coupling through 10, 12, to the base of Q, turns Q on, completing a cycle.

Control is established by feedback from the output that causes a drain on the charge stored in the base of Q. The more that is removed,...