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Field Effect Transistor Drive Circuit

IP.com Disclosure Number: IPCOM000082004D
Original Publication Date: 1974-Sep-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Simi, VM: AUTHOR

Abstract

A high-voltage gating signal is developed at node N2 to gate driving field-effect transistor (FET) device Q4 to a full ON state, to apply supply voltage VH to output node N3. Required input signals T1 and T2 are developed from a suitable source whenever an output cycle at node N3 is desired. Input signal T1 renders FET devices Q1 and Q5 conductive to, respectively, lower both nodes N2 and N3 to ground potential, thereby turning OFF drive device Q4 and normalizing node N3. Input signal T2 can be derived by a delay or extension of signal T1.

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Field Effect Transistor Drive Circuit

A high-voltage gating signal is developed at node N2 to gate driving field- effect transistor (FET) device Q4 to a full ON state, to apply supply voltage VH to output node N3. Required input signals T1 and T2 are developed from a suitable source whenever an output cycle at node N3 is desired. Input signal T1 renders FET devices Q1 and Q5 conductive to, respectively, lower both nodes N2 and N3 to ground potential, thereby turning OFF drive device Q4 and normalizing node N3. Input signal T2 can be derived by a delay or extension of signal T1.

Upon removal of input signal T1, capacitor C1 stores charge due to conduction through FET device Q3. Removal of input T2 removes node N1 from ground and rapidly causes the energy stored in capacitor C1 to raise the potential at node N2, as enhanced by the regenerative effect of FET device Q6. Current supply FET Q2 is shown as continuously conducting, however, for greater efficiency, the gate to device Q2 can be clocked at the termination of signal T1 to minimize current drain during the normalization of node N3.

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