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Self Resetting Logic Circuit

IP.com Disclosure Number: IPCOM000082047D
Original Publication Date: 1974-Sep-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 33K

Publishing Venue

IBM

Related People

Herrell, DJ: AUTHOR [+2]

Abstract

Fig. 1 shows a logic circuit employing a Josephson tunnelling device (JTD). In its zero voltage state current I(g) flows through the Josephson device. When control currents, such as I(c1), I(c2), and I(c3) are present, the JTD switches to its nonsuperconducting state and current is shifted into the strip lines 10A, 10B which have characteristic impedance Z(0). The strip lines are terminated in a resistance 2Z(0). Thus, depending upon the presence of input signals in the control lines, current will be delivered to the load resistor 2Z(0).

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Self Resetting Logic Circuit

Fig. 1 shows a logic circuit employing a Josephson tunnelling device (JTD). In its zero voltage state current I(g) flows through the Josephson device. When control currents, such as I(c1), I(c2), and I(c3) are present, the JTD switches to its nonsuperconducting state and current is shifted into the strip lines 10A, 10B which have characteristic impedance Z(0). The strip lines are terminated in a resistance 2Z(0). Thus, depending upon the presence of input signals in the control lines, current will be delivered to the load resistor 2Z(0).

The inherent hysteresis of the current-voltage characteristic of a Josephson device generally necessitates that the gate current I(g) of the device be blocked, in order to reset the Josephson device to its zero voltage state. For combinatorial logic, this means that a large number of individually timed gate pulses must be provided with a consequent reduction of overall speed and tolerance in the logic circuit.

Fig. 2 shows a typical I(c) - I-V characteristic of a Josephson tunnelling logic gate, which could be the circuit of Fig. 1. If a constant-gate current I is present, the combination of control currents having a net value I'(c) will cause the maximum Josephson current I(go) in the device to fall below the constant-gate current I(g). At this time the junction will switch to its finite voltage state where V = 2 delta (superconducting band gap) along a load line BA, determined by the impedances Z(s) and Z(o). The impedance Z(s) is a characteristic impedance of the input transmission line to the Josephson device, while Z(o) is the characteristic impedance of a transmission line 10A or 10B. That is, the equation for the load line BA is 1 over R(load) = 1 over 2Z(s) + 1 over 2Z(o).

Generally, the junctio...