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Repairable Large Scale Integrated Logic Unit

IP.com Disclosure Number: IPCOM000082059D
Original Publication Date: 1974-Sep-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Roth, JP: AUTHOR

Abstract

In the publication "Computer Design Architecture II", J. P. Roth, RA 48, March 1, 1973, pp. 114-132, published by the IBM Corporation, there is described a universal functional object which can be employed for realizing any function, combinational or sequential, in a single universal function scheme. Such universal functional object is addressed to the problem of the proliferation of the number of parts such as cards, chips, etc. necessary for the conventional implementation in large-scale integration (LSI) technology of the computer system (terminal or peripheral systems). This universal functional object is a solution primarily of the so-called "parts-number explosion". While this scheme is very efficacious for its intended purpose, the disadvantage presented thereby is that it requires a large amount of hardware.

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Repairable Large Scale Integrated Logic Unit

In the publication "Computer Design Architecture II", J. P. Roth, RA 48, March 1, 1973, pp. 114-132, published by the IBM Corporation, there is described a universal functional object which can be employed for realizing any function, combinational or sequential, in a single universal function scheme. Such universal functional object is addressed to the problem of the proliferation of the number of parts such as cards, chips, etc. necessary for the conventional implementation in large-scale integration (LSI) technology of the computer system (terminal or peripheral systems). This universal functional object is a solution primarily of the so-called "parts-number explosion". While this scheme is very efficacious for its intended purpose, the disadvantage presented thereby is that it requires a large amount of hardware.

To overcome the problem of this proliferation of hardware, there is described herein a LSI unit which also is advantageously employed as a universal functional object, but wherein there is provided a substantially beneficial decrease in the amount of required circuitry with a retention of a reliability comparable to that of the aforedescribed universal functional object.

There is first reviewed the concept of universal AND's (UA) and universal OR's (UV). Reference accordingly is made to Fig. 1 wherein there is shown a universal AND circuit for two inputs a, b. The inputs are assumed to come both complemented and uncomplemented. The circles symbolize memory cells which suitably can be interconnected as a shift register.

Let it be assumed, for example, that it is desired that the universal AND realize the function a, b. Then, in the memory cells feeding the AND circuits which are also fed by a, a, b, b, respectively, there are inserted the bits 1 0 0 1.

As the tabulation in Table I hereinbelow indicates, there is a clear one-to-one correspondence between memory cell arrays and the desired conjunction: Table I

Conjunction Memory Cell Contents

a a b b

a b 1 0 1 0

a b 1 0 0 1

a b 0 1 1 0

a b 0 1 0 1

The contents of these memory cells are suitably termed connection words.

In a similar manner, the universal OR is defined as depicted in Fig. 2, wherein there is shown a two-input universal OR circuit. Table II hereinbelow illustrates the connection word for the...