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Analog To Digital Converter using Josephson Tunneling Circuits

IP.com Disclosure Number: IPCOM000082063D
Original Publication Date: 1974-Sep-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Anacker, W: AUTHOR

Abstract

An analog-to digital converter 1 with Josephson tunneling gates is shown in Fig. 1. A number of multicontrolled gates 2 are connected serially to a gate current supply 3. One control line 4 common to all gates carries the analog signal in parallel with the gate current. A second control line 5 of each gate 2 serves as an individual bias line carrying multiples of units of currents, in accordance with the dynamic range of the analog signal. The bias currents are applied antiparallel to the analog signal.

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Analog To Digital Converter using Josephson Tunneling Circuits

An analog-to digital converter 1 with Josephson tunneling gates is shown in Fig. 1. A number of multicontrolled gates 2 are connected serially to a gate current supply 3. One control line 4 common to all gates carries the analog signal in parallel with the gate current. A second control line 5 of each gate 2 serves as an individual bias line carrying multiples of units of currents, in accordance with the dynamic range of the analog signal. The bias currents are applied antiparallel to the analog signal.

With the bias currents i to 17i shown in Fig. 1, a biasing situation exists for each gate in relation to the analog signal amplitude as indicated in Fig. 2. Since the analog signal and bias subtract algebraically, all but one or two gates 2 are biased outside of their gain curves shown at 6 in Fig. 2. Thus, when the gate current is applied to all gates 2, after the proper analog signal level is established in control line 4, all gates but those for which the gate current and the effective control current fall inside the gain curves 6 switch. As indicated in Fig. 2, for three analog signals, 0, 3 and 12, gates A and B, gate C and gates G and H, respectively, will be the gates which will not switch. The operating points for these gates remains inside their gain curves 6, as shown at 7 and 8, 9 and 10 and 11, respectively.

The table on the bottom of Fig. 2 displays the conditions of the gates A to I for a...