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Generation of Associative Logic Arrays

IP.com Disclosure Number: IPCOM000082070D
Original Publication Date: 1974-Sep-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 23K

Publishing Venue

IBM

Related People

Ellozy, HA: AUTHOR [+3]

Abstract

There is a known technique which accepts a logic design consisting of primitive acyclic logic cells interconnected in arbitrary fashion with no feedback introduced, and transforms this multiple level logic with many inputs and outputs suitably termed M and R, respectively, into two-level logic design which is functionally equivalent to the original. Such two-level design is known as an Associative Logic Array (ALA). A predecessor term for an ALA is a "cover" which is discussed in "Computer Design/I", J. P. Roth, RA 45, December 22, 1972, and "Computer Design Architecture II", J. P. Roth, RA 48, March 1, 1973, both of these publications being published by the IBM Corporation.

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Generation of Associative Logic Arrays

There is a known technique which accepts a logic design consisting of primitive acyclic logic cells interconnected in arbitrary fashion with no feedback introduced, and transforms this multiple level logic with many inputs and outputs suitably termed M and R, respectively, into two-level logic design which is functionally equivalent to the original. Such two-level design is known as an Associative Logic Array (ALA). A predecessor term for an ALA is a "cover" which is discussed in "Computer Design/I", J. P. Roth, RA 45, December 22, 1972, and "Computer Design Architecture II", J. P. Roth, RA 48, March 1, 1973, both of these publications being published by the IBM Corporation.

A difficulty encountered with the aforementioned technique is that some of the intermediate covers, and which require intermediate memory storage, become quite large. Consequently, the amount of time required for each corresponding intermediate operation becomes undesirably large. Such inordinate requirements for intermediate memory may occur even though the final cover, the ALA, may be of quite reasonable size.

In the technique described herein, there is effected the decreasing of the size of an intermediate cover whenever it becomes unacceptably large. Thus, let s be the size of the intermediate cover and S its maximum acceptable size. Then, whenever s exceeds S, the intermediate cover-decreasing routine is invoked to reduce the size of the resulting equivalent cover or intermediate ALA.

There is assumed that there is given an associative logic array with the primary input variables b pi2,...,pim and primary output variables po2,...,pon. In the application of the technique, the primary output variables, po, are the primary outputs po of the design logic being transformed into an ALA. The primary inputs pi are, in general, an assemblage of variables associated with internal lines of the logic design.

The functioning of the intermediate-cover-decreasing routine, however, is independent of the origin or interpretation of its pi's and po's.

The ALA may be considered as depicted hereinbelow:

(Image Omitted)

In considering the technique described herein, it produces an associative logic array equivalent to the original logic design, from a detailed description of the logic design. The intermediate-cover-size-decreasing routine is a g...