Browse Prior Art Database

Multiplex Digital Power System Controller

IP.com Disclosure Number: IPCOM000082104D
Original Publication Date: 1974-Oct-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 81K

Publishing Venue

IBM

Related People

Clark, MJ: AUTHOR

Abstract

The drawings illustrate a method and means of performing multifunctions in a data processing system, by switching different types of multiplexor units during power on, power monitoring, power off and other sequences of control steps.

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Multiplex Digital Power System Controller

The drawings illustrate a method and means of performing multifunctions in a data processing system, by switching different types of multiplexor units during power on, power monitoring, power off and other sequences of control steps.

In Fig. 1, either manually operable controls 1 or a programmed service processor 2 initiate a power on sequence for the associated group of processors 3 and 4, together with their associated storage module 5, storage module controller 6 an I/O controller 7. The power up sequence is achieved by a four-bit digital counter 8 which steps through counts 1-16 in sequence.

A decode mechanism 9-1 translates the counter output to one of sixteen lines 10-1 to 10-16. The sixteen lines are coupled to respective FETs (field-effect transistors) in a power up control multiplexor 11-1, a power down control multiplexor 12-1 and a voltage compare monitor switching unit 13-1. The outputs of the counter 8 are also coupled to decode mechanisms 9-2 to 9-n, which in turn control similar multiplexors and voltage compare switching units.

Each of the voltage compare switching units 13-1 to 13-n is connected in sequence to an A/D converter 15, by way of a decode circuit 16 and an associated 4-digit binary counter 17. The counter 17 is advanced one increment each time that the counter 8 is incremented through its entire sequence of sixteen counts. When counter 17 is in its initial state, it gates the output of the counter 8 is incremented through its entire sequence of sixteen counts. When counter 17 is in its initial state, it gates the output of the voltage compare switching unit 13-1 to A/D converter 15. While counter 17 is in this state, counter 8 sequences through each of its sixteen states; and it turns on transistors in 13-1 to sequentially gate each of the sixteen inputs (e.g., voltage levels) of switching unit 13 to the A/D converter 15.

The output of the A/D converter 15 is applied to one side of a compare register 18; and the processor 2 applies the expected results into the other side of 18. In the event that the expected results and the output of the A/D converter 15 match, a monitoring control routine continues in the normal manner in processor 2. In the event of a miscompare, an error routine program is initiated in processor 2.

The power up multiplexor 11-1, illustrated partially in Fig. 2, includes a respective FET switch 35-1 to 35-16 for each of a plurality of functions, which must be performed to turn on the various power supplies for the system. Each FET in the multiplexor 11-1 sets a corresponding latch, such as 21, when it is turned on, and when the corresponding input line 10-1 is energized by the counter 8 via decode circuit 9.

The FETs are turned on by applying an input signal to their gate electrodes by way of a control line 22 and an inverter 36. When FET 35-1 sets the latch 21, the latch causes AC power to be applied to the input controls for AC/DC converters...