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Fabricating Complementary Field-Effect Transistor Devices

IP.com Disclosure Number: IPCOM000082114D
Original Publication Date: 1974-Oct-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 106K

Publishing Venue

IBM

Related People

Antipov, I: AUTHOR [+2]

Abstract

In this process, a monocrystalline silicon substrate 10 receives a blanket phosphorous implant forming an N region 12 and a boron pocket implant forming P pocket 14 (Fig. 1). A thin SiO(2) layer 16, Fig. 2, is formed on the surface of substrate 10, either by thermal oxidation or pyrolytic deposition having a thickness on the order of 200 angstroms. A blanket layer 18 of silicon nitride, preferably having a thickness in the range of 300-500 angstroms is deposited on the surface of layer 16, and a layer 20 of pyrolytic SiO(2) is subsequently deposited on layer 18.

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Fabricating Complementary Field-Effect Transistor Devices

In this process, a monocrystalline silicon substrate 10 receives a blanket phosphorous implant forming an N region 12 and a boron pocket implant forming P pocket 14 (Fig. 1). A thin SiO(2) layer 16, Fig. 2, is formed on the surface of substrate 10, either by thermal oxidation or pyrolytic deposition having a thickness on the order of 200 angstroms. A blanket layer 18 of silicon nitride, preferably having a thickness in the range of 300-500 angstroms is deposited on the surface of layer 16, and a layer 20 of pyrolytic SiO(2) is subsequently deposited on layer 18.

To achieve the structure shown in Fig. 3, a photoresist layer is deposited on the surface of the substrate 10, and the resist layer exposed to leave areas over the intended device area. The exposed portions of SiO(2) layer 20 are then subtractively etched, the resist removed, and the exposed areas of Si(3)N(4) layer 18 removed using the retained areas of layer 20 as a mask.

As indicated in Fig. 4, the substrate 10 is again covered by a photoresist layer, the resist layer exposed and developed to retain areas defining the gate regions of the device, and the remaining portions of layer 20 subtractively etched to form the gate oxide region 22. At this time, the remaining exposed regions of layer 16 are also removed.

As indicated in Fig. 5, the exposed areas of the monocrystalline silicon wafer 10 are oxidized forming oxide regions 24. At this time, a...