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Fabricating High Voltage Power Transistors

IP.com Disclosure Number: IPCOM000082115D
Original Publication Date: 1974-Oct-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Anantha, NG: AUTHOR [+2]

Abstract

In this process, discrete high-voltage power transistors are produced with deep-base regions having step-like profiles, without the conventional long drive-in heat cycle normally used to produce power transistors.

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Fabricating High Voltage Power Transistors

In this process, discrete high-voltage power transistors are produced with deep-base regions having step-like profiles, without the conventional long drive- in heat cycle normally used to produce power transistors.

In this process, the starting material is a monocrystalline arsenic doped substrate having a resistivity of approximately 0.01 ohms/cc. An epitaxial layer is grown on the substrate that has a resistivity of approximately 30 ohms/cm and a thickness of approximately 100 microns. A silicon dioxide layer is grown on the surface of the epitaxial layer and selectively etched, leaving base diffusion window openings therein. A boron impurity is introduced through the openings either by diffusion or ion implantation.

After the surface has been oxidized, the entire masking layer is stripped which provides a small step in the top silicon surface of the epitaxial layer for later use as a mask alignment reference. An additional epitaxial layer, approximately 10 microns in thickness, is then grown on the previously deposited layer also having a resistivity on the order of 30 ohm/cm. A masking SiO(2) layer is then grown and etched using photolithographic techniques, to open the base window over the previously formed window.

A boron impurity is introduced through the window either by diffusion techniques or ion implantation and the surface reoxidized. The reoxidized surface is then etched using photolithographic techniques to...