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FET Stray and Coupling Capacitance Equalization Technique

IP.com Disclosure Number: IPCOM000082130D
Original Publication Date: 1974-Oct-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Sonoda, G: AUTHOR

Abstract

This is a technique for equalizing field-effect transistor (FET) stray and coupling capacitance in a FET memory array.

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FET Stray and Coupling Capacitance Equalization Technique

This is a technique for equalizing field-effect transistor (FET) stray and coupling capacitance in a FET memory array.

Capacitive loading and noise coupling into each of a pair of bit lines used for differential sensing can differ significantly, due to mask shifts when designing in a nonself-aligned metal gate FET process. When sense currents are extremely small (in the order of 10 microamps), these mask shifts cause a significant performance degradation.

In the present case, assume a storage array chip consisting of two array halves, a left-hand array and a right-hand array. These array halves are separated by bit decoders, not shown. By crossing the bit line pairs in each array half at midlength as shown, unequal stray capacitance and coupling capacitance caused by mask shift will be equalized to allow sensing of very small signals. The type of mask shift compensated for includes rotational as well as lateral shifts in the X and Y dimensions.

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