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Multiple Threshold IGFET Ternary Circuits

IP.com Disclosure Number: IPCOM000082131D
Original Publication Date: 1974-Oct-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Dansky, AH: AUTHOR

Abstract

Ternary logic functions are implemented through the use of insulated gate field-effect transistor (IGFET) circuits, containing devices with two different threshold voltages.

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Multiple Threshold IGFET Ternary Circuits

Ternary logic functions are implemented through the use of insulated gate field-effect transistor (IGFET) circuits, containing devices with two different threshold voltages.

Ternary logic requires three voltage levels which can be obtained by using IGFET devices, with different threshold voltages in the same circuit and selecting the appropriate width-to-length (W/L) ratios for each device. There are several techniques for obtaining devices with different threshold voltages. One technique is to vary the gate oxide thickness during processing. Another technique is to vary the source-to substrate voltage which requires isolating the devices into two separate regions (pockets). Still another technique is to use ion implantation to vary the background doping, as presently used to obtain depletion load devices.

To implement ternary functions, the depletion device is used as the active device with the lower threshold voltage (V(T)1) and the enhancement mode device as the active device with the higher threshold voltage (V(T)2).

In the figures, Fig. 1 illustrates the voltage and threshold levels for a particular ternary logic state. Positive threshold voltages have been chosen for algebraic simplicity, even though threshold voltages could be negative. Fig. 2A illustrates an exemplary circuit, Fig. 2B refers to the logic definitions corresponding to that circuit, while Fig. 2C describes the design conditions for the circuit of 2A....