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Browse Prior Art Database

Gated Output Word Decoder

IP.com Disclosure Number: IPCOM000082133D
Original Publication Date: 1974-Oct-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Askin, HO: AUTHOR [+3]

Abstract

This is a decoder for a field-effect transistor (FET) memory, in which the word line may be biased to any desired level by a bias circuit.

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Gated Output Word Decoder

This is a decoder for a field-effect transistor (FET) memory, in which the word line may be biased to any desired level by a bias circuit.

Devices 1 to 5 of this word decoder operate as prior word decoders. Device 3 charges nodes A and B to +V voltage minus a threshold voltage during the restore part of the cycle. During an unselected cycle, one or more of devices 1-1 to 1-N (number of devices dependent on number of decode or storage address registers (SAR's)) turn on and discharge node A. Since its drain voltage is at +V minus a threshold voltage, device 2 turns on and discharges node B.

Before this time, Phi 1 has switched to an up level placing node D at +V voltage minus a threshold voltage. Phi 2 is now switched to an up level. Since node B is down node C stays down, device 7 is on so the word line stays down. Any positive voltage coupled to the word line is discharged through devices 7, 5, 2 and 1.

During a selected cycle the SAR's are all down. Nodes A and B have been charged during restore (as during an unselected cycle). Since the SAR inputs are down, devices 1-1 to 1-N stay off leaving nodes A and B charged. At this time, node D has been raised to an up level by Phi 1. Since node B is up, device 4 is on, thus charging node C. Capacitor C1 feeds back voltage to node B, raising node B above Phi 2 (up) plus one threshold voltage. Thus, node C rises to Phi 2 voltage. The rising voltage on node B has turned off device 2, isolating th...