Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Cross Coupled Latch for Memory Sensing

IP.com Disclosure Number: IPCOM000082134D
Original Publication Date: 1974-Oct-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Lee, JM: AUTHOR

Abstract

This circuit includes a second cross-coupled latch having field-effect transistors (FET's) 11 and 12 for further improving the performance of a FET memory.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Cross Coupled Latch for Memory Sensing

This circuit includes a second cross-coupled latch having field-effect transistors (FET's) 11 and 12 for further improving the performance of a FET memory.

The use of cross-coupled latches, such as illustrated by FET's 1 and 2 for aiding the discharge of bit lines, is well known. Transistors 3 and 4 are alternately actuated to achieve the desired race condition in the cross-coupled latch. Transistors 5 and 6 gate the resultant differential signal onto common bit line 0 and common bit line 1.

Transistors 1 and 2 are small width-to-length (W/L) ratio devices to minimize the loading on the bit lines. Their function is to amplify the current available from the cell to set the information of the cell onto the common bit lines.

The occurrence of the phase B pulse at the gate of transistor 10 turns on transistors 10 and 14, while transistors 13 and 15 are turned off, thereby actuating the second cross-coupled latch consisting of FET's 11 and 12. The resultant state of this second latch is sensed at the gate of FET 9 which, together with transistors 7 and 8 and feedback capacitor CFB, forms a sense amplifier providing an output at node B.

Thus, the second cross-coupled latch, triggered with the appropriate timing pulse, improves the power/performance ratio of the FET memory array.

1

Page 2 of 2

2

[This page contains 4 pictures or other non-text objects]