Browse Prior Art Database

Memory System Fabrication Using Laser Formed Connections

IP.com Disclosure Number: IPCOM000082149D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Cook, PW: AUTHOR [+2]

Abstract

In conventional approaches to higher levels of integration in logic, the limits are imposed by the approximately exponential failures in yield. This results in an exponential increase in silicon cost. Historically, large machines are made out of smaller good chips selected out of total product, packaged and assembled as a hierarchy of chip module, card, board, etc. The ability to make laser formed connections open a new dimension in integrated circuit fabrication. Specifically, it is possible to fabricate integrated circuits with redundant parts and employ the laser to interconnect working parts. The implications of this are significantly higher levels of integration, with the elimination of possibly several levels of packaging.

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Memory System Fabrication Using Laser Formed Connections

In conventional approaches to higher levels of integration in logic, the limits are imposed by the approximately exponential failures in yield. This results in an exponential increase in silicon cost. Historically, large machines are made out of smaller good chips selected out of total product, packaged and assembled as a hierarchy of chip module, card, board, etc. The ability to make laser formed connections open a new dimension in integrated circuit fabrication. Specifically, it is possible to fabricate integrated circuits with redundant parts and employ the laser to interconnect working parts. The implications of this are significantly higher levels of integration, with the elimination of possibly several levels of packaging.

The basic concept is illustrated in the figure. Shown is a part of a VLSI (Very Large Scale Integration) semiconductor chip 1 consisting of a cluster of virtual chips 2. Within a cluster all virtual chips 2 are identical, and only one is required to implement the cluster's function Thus, redundancy is provided at the level of virtual chips. Interconnection tracks 3 are provided in what would normally be the pad and kerf area of the virtual chips; however, prior to personalization there are no direct connections between virtual chips 2 and the tracks 3.

Indirect connections T1, T2 for test are provided through series devices 4; while only two devices 4 per chip are shown, the concept generalizes to many devices 4 and many test lines per virtual chip. Gates 5 of such series devices 4 for a given virtual chip 2 are common, thus allowing an individual virtual chip 2 to be switched into the interconnections 3 for test purposes. Tracks 3 used for test would be shared among the virtual chips and possibly also used as part of the final interconnection pattern. It is thus possible to effectively probe a single isolated virtual chip 2, using pads at the periphery of the entire array, thus simplifying test problems. Series devices 4 are turned on only during the test of the corresponding virtual chips 2.

To interconnect working chips, added leads 6 are also provided. These leads cross the interconnection tracks 3, but initially are not connected at any point. Subsequent to test, a laser is used to form connections between working virtual chips 2 and certain of interconnection tracks 3, shown in the figure as signal tracks S1, S2....