Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

NOR OR Gate for Josephson Tunneling Memory

IP.com Disclosure Number: IPCOM000082155D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Herrell, DJ: AUTHOR

Abstract

A NOR-OR gate utilizing Josephson junctions is schematically shown in Fig. 1. The operation is as follows. Initially, consider both Josephson junctions J1, J2 to be in the superconducting state. If control lines A, B or C associated with junction J1 carries a signal representative of a digital "1", then J1 switches to V not = 0. The load line presented to J1 is essentially equal to the resistor R1, which in Fig. 1 shunts Josephson junctions J1, J2. The current through resistor R1 is V1/R1, where V1 is obtained by the intersection of the load line with the normal characteristics of Josephson junction J1. Whereas the initial gate current to junctions J1, J2 was I, this value is now reduced to I - V1/R1.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

NOR OR Gate for Josephson Tunneling Memory

A NOR-OR gate utilizing Josephson junctions is schematically shown in Fig.
1. The operation is as follows. Initially, consider both Josephson junctions J1, J2 to be in the superconducting state. If control lines A, B or C associated with junction J1 carries a signal representative of a digital "1", then J1 switches to V not = 0. The load line presented to J1 is essentially equal to the resistor R1, which in Fig. 1 shunts Josephson junctions J1, J2. The current through resistor R1 is V1/R1, where V1 is obtained by the intersection of the load line with the normal characteristics of Josephson junction J1. Whereas the initial gate current to junctions J1, J2 was I, this value is now reduced to I - V1/R1. In the NOR gate implementation, J2 only has one control line associated with it which carries the timing bias necessary for inversion. The amplitude of the timing bias necessary for correct operation is: if I(j2) = I then J2 switches to V not = 0 if I(j2) = I - V1/R1, then J2 remains in a V=0 state. This is the NOR operation.

For the OR operation, the input lines A, B, C are disregarded while the second gate, J2, now has three control lines. This is exactly the same as present designs of the multicontrol OR gate, except that there is an undriven gate in series with the logic gate. Obviously, by presenting the two junctions each with multicontrols, various mixtures of OR and NOR can be obtained with this one gate. Consider Fig. 2, this may be used for the implementation of (A+B . (C+D)) +
C.D, since C.D in general will be sufficient to switch J2 irrespective of the state of J1. The inputs to the J2 gate have to be delayed with respect to the inputs of J1.

Certain design criteria have to be met to ensure correct operation. These will be summarized mainly for the NOR implementation. Referring to Fig. 1, assuming a gain curve slope of -1 (nonlinear in line gates) it can be shown as follows: I> I(m)(0)(1) - i(0) J1 switches with a control of i(0). I-V1/R1 < I(m)(0)(2) - i(0) J2 does not switch on bias if J1 already switched. I-V2(R1+R2) over R1 R2 > Imin(2) J2 remains nor...