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MOSFET Devices with High Gate Dielectric Integrity

IP.com Disclosure Number: IPCOM000082159D
Original Publication Date: 1974-Jun-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Fowler, AB: AUTHOR [+4]

Abstract

Described is a fabrication technique to achieve high gate dielectric reliability in metal-oxide semiconductor field-effect transistors (MOSFET) devices. The technique consists of a FET fabrication process to implement the beneficial effects of a preoxidation hydrogen anneal of Si wafers. When performed at high temperatures (1100-1300 degrees C), the H(2) step greatly reduces the breakdown defect density in subsequently grown silicon dioxide. The constraints on the process are: 1) Oxidation must immediately follow H(2) anneal. 2) Diffusions or implantations must be performed after the high temperature H(2) step to avoid junction spread. The steps of the technique are as follows: 1. Wafer cleaning. 2. Hydrogen anneal - about 1/2 hr. at temperatures over 1200 degrees C. 3.

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MOSFET Devices with High Gate Dielectric Integrity

Described is a fabrication technique to achieve high gate dielectric reliability in metal-oxide semiconductor field-effect transistors (MOSFET) devices. The technique consists of a FET fabrication process to implement the beneficial effects of a preoxidation hydrogen anneal of Si wafers. When performed at high temperatures (1100-1300 degrees C), the H(2) step greatly reduces the breakdown defect density in subsequently grown silicon dioxide. The constraints on the process are:
1) Oxidation must immediately follow H(2) anneal.
2) Diffusions or implantations must be performed after the

high temperature H(2) step to avoid junction spread.

The steps of the technique are as follows:
1. Wafer cleaning.
2. Hydrogen anneal - about 1/2 hr. at temperatures over 1200

degrees C.
3. Thin gate oxide growth in either O(2) or HCl + O(2).
4. Deposition of thin nitride layer - for later use as etching

mask and stopper.
5. Deposition of thick pyrolytic oxide for field region.
6. Etching of pyrooxide down to nitride in device areas.
7. Standard self-aligned gate processing - for instance,

poly Si gate deposition; nitride and oxide etch over

source and drain; doping of source, drain and gate using

drain; doping of source, drain and gate using ion implantation

or POCL(3) or As source; metallization; protective coating.

Two alternative ways to achieve high doping in the field region are possible:
1) use a more heavily doped (>10/16/ /c...