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Truncating Internal Power Columns on Ordered Grid Arrays

IP.com Disclosure Number: IPCOM000082182D
Original Publication Date: 1974-Oct-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 6 page(s) / 204K

Publishing Venue

IBM

Related People

Brechling, GE: AUTHOR [+6]

Abstract

Artwork for large-scale integration (LSI) devices may be generated in an ordered grid layout as described in USP 3,475,621. The predefined location of devices and power buses in the ordered grid array does not make efficient use of the chip area. Truncating or bending power columns in the layout facilities placement of functional logic circuits, e.g., decoders, program logic arrays and the like.

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Truncating Internal Power Columns on Ordered Grid Arrays

Artwork for large-scale integration (LSI) devices may be generated in an ordered grid layout as described in USP 3,475,621. The predefined location of devices and power buses in the ordered grid array does not make efficient use of the chip area. Truncating or bending power columns in the layout facilities placement of functional logic circuits, e.g., decoders, program logic arrays and the like.

Fig. 1 shows a semiconductor chip 10 having terminal pads 12 disposed about the periphery of the chip. A power distribution system 14 includes a distribution bus 16 and vertical power columns 18. The elements 16 and 18 comprise one or more phase lines; a reference voltage line, and a supply voltage line. Fig. 1 shows the vertical power columns shifted and bent to define areas in which functional logic elements 20 may be located.

Fig. 2 shows details of a vertical power column that is bent about a functional logic unit 22. Power column 24 is adapted to be contacted to power column 26, which only extends part of the way between the distribution bus 16, not shown. Interconnections between bus 24 and 26 may be either by metal 28 or diffusions
30. Metal contacts 32 form the interconnection between the diffusion and metal lines.

An algorithm, shown in Figs. 3A to 3F, may be programmed to automatically generate artwork for fabricating semiconductors having vertical power columns altered in an ordered grid array, to make more efficient utilization of the area available in a semiconductor device. The following information is provided as an input to the algorithm to achieve a desired configuration for a vertical power column:
1. The internal vertical power column to be altered.
2. The type of shift or deletion in a power column.
3. The direction in which the vertical power column is to be

oriented.
4. The `Y' coordinate of the orientation above and/or below the

functional logic unit.
5. The `X-low coordinate of the vertical p...