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Dynamic Logic Tester for Large Scale Integration

IP.com Disclosure Number: IPCOM000082184D
Original Publication Date: 1974-Oct-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Bonar, RG: AUTHOR [+2]

Abstract

Testing speed for large-scale integration (LSI) devices may be increased by accessing groups of words in parallel and converting to a stream of serial words. The memory may be fabricated from inexpensive, low-performance technology while the conversion circuitry can be fabricated from high-performance circuits.

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Dynamic Logic Tester for Large Scale Integration

Testing speed for large-scale integration (LSI) devices may be increased by accessing groups of words in parallel and converting to a stream of serial words. The memory may be fabricated from inexpensive, low-performance technology while the conversion circuitry can be fabricated from high-performance circuits.

The memory operation and conversion circuits provide an apparent test speed which is N times faster than the memory cycle, where N is the number of words read out in a word group. Tester operation can provide a large number of consecutive words at a very fast rate, for application in supplying test patterns to a dynamic test system.

Words are read from memories 10/1/ through 10/N/ under control of address generator 14, such that the first word read in each memory is available to registers 11/1/ through 11/N/ at the time shift 1 (see Fig. 2) is valid. Memories 10/1/ through 10/N/ may also be a single memory, accessing sufficient bits to form words 1 through N, each of which contains the correct number of bits as defined for an output word. Words 1 through N are then shifted to registers 121 through 12N at the time shift 2 is valid.

Cycle control 15 causes words 1 through N to be gated by AND circuits 16 presenting data serial-by-word through OR 17 to an output bus. Counter 18 causes the address generator 14 to increment and causes sequential operation of the cycle control 15.

This circuit arrangement permits...