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Centralized Interval Timer and Event Counter

IP.com Disclosure Number: IPCOM000082198D
Original Publication Date: 1974-Oct-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 4 page(s) / 136K

Publishing Venue

IBM

Related People

Schettl, MD: AUTHOR [+2]

Abstract

An interval timer and event counter (ITEC) is provided in an I/O microprocessor controller (IOC) to service I/O devices attached to the IOC. Except during the loading of the timers and counters within ITEC and when an interrupt occurs due to a time out or an event occurrence, ITEC operates without microprocessor attention, although always under control of the microprocessor. The timing and counting functions are programmable and can be changed at any time by the microprocessor. The timers and counters forming the ITEC are ranked in priority according to their relative positions in the local storage register (LSR) of the IOC.

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Centralized Interval Timer and Event Counter

An interval timer and event counter (ITEC) is provided in an I/O microprocessor controller (IOC) to service I/O devices attached to the IOC. Except during the loading of the timers and counters within ITEC and when an interrupt occurs due to a time out or an event occurrence, ITEC operates without microprocessor attention, although always under control of the microprocessor. The timing and counting functions are programmable and can be changed at any time by the microprocessor. The timers and counters forming the ITEC are ranked in priority according to their relative positions in the local storage register (LSR) of the IOC.

IOC 20, Fig. 1, is incorporated in a computer system including storage 10 and central processing unit (CPU) 15 with input/output (I/O) devices 25 connected to IOC 20. ITEC 30 located in IOC 20 functions to keep track of events occurring within I/O devices 25 and to provide time duration signals thereto.

IOC 20, is shown schematically in Fig. 2 with some of the registers 21 being used by ITEC 30 when they are not being used by IOC 20. IOC 20 only uses local storage registers 21 during approximately half of a cycle time. The remainder of the IOC 20 cycle is used for operating arithmetic and logic unit (ALU) 22, and performing control or housekeeping functions.

During the portion of a cycle when IOC 20 is not using registers 21, two bytes are read from registers 21 which had been loaded under control of IOC 20. One byte is the count byte and the other is a control byte. The count and control bytes, Fig. 3, are applied to eight-bit incrementor 31 and to control byte decode logic 32, respectively.

The count byte register of registers 21 is loaded under the control of the IOC with 0's or with the 2's complement of the number of events to be counted, depending upon whether or not an interrupt is to occur after a predetermined number of events, or if internal clock pulses have been counted. The 2's complement is loaded if an interrupt is to occur.

The significance of the bits forming the control byte is set forth in Table 1. The control byte, upon being decoded, and edge detect logic 36 determine if the present count should be incremented by 1. In any event, the count and control bytes are returned from incrementor 31 and decode 32 to their respective registers. The registers 21 containing the count and control bytes, are addressed by counter 33 via gate 34 and control 23 which is part of IOC 20. Counter 33 is incremented at the end of each cycle. Control 23 provides a clock pulse for advancing counter 33 and for enabling internal timer 35, to repetitively provide timing signals of different time durations.

The time duration signals are applied to edge detect logic 36 along with external event inputs from I/O devices 25. The edge detect logic...