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Translator for Run Length Code

IP.com Disclosure Number: IPCOM000082216D
Original Publication Date: 1974-Oct-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 65K

Publishing Venue

IBM

Related People

Miessler, M: AUTHOR

Abstract

Run length limited coding (or RLL coding) requires that each 1 in a coded binary sequence must be separated from the nearest adjacent 1 by at least a minimum number of 0's, in order to ensure freedom from intersymbol interference during recording or transmission, but by not more than a maximum number of 0's to permit self-clocking. In a translator described below the minimum is two 0's and the maximum is eight 0's, and consequently the RLL code is called a (2,8) Run Length Limited code.

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Translator for Run Length Code

Run length limited coding (or RLL coding) requires that each 1 in a coded binary sequence must be separated from the nearest adjacent 1 by at least a minimum number of 0's, in order to ensure freedom from intersymbol interference during recording or transmission, but by not more than a maximum number of 0's to permit self-clocking. In a translator described below the minimum is two 0's and the maximum is eight 0's, and consequently the RLL code is called a (2,8) Run Length Limited code.

Fig. 1 shows the translator which consists of a read-only memory 1 which is accessed by addresses generated by a shift register (SR1) 2. Data to be translated is supplied through an input gate 3 which consists of an inverter gate I, a pair of AND gates A1, A2 and an 0R gate 0. If ordinary data is to be translated to (2,8) RLL coded data a signal W on line 4 activates AND gate A1, to allow ordinary data to enter shift register SRl which has been previously set to all 1's. Alternatively, if RLL coded data is to be translated to ordinary data AND gate A2 is activated.

Data in shift register SR1 addresses memory 1 which produces translations on lines 0(1) to 0(8). Output lines 0(1) and 0(2) indicate either an invalid translation (1,1) or the length of a valid translation. Output signals on lines 0(1) to 0(8) are entered into a shift register (SR2) 5 under the control of gates G1 to G5. The gates G1 to G5 are controlled by a decoder 6 to allow the passage of signals on their associated lines, as will be described below.

Valid translations in shift register 5 are shifted out through an output gate 7. Output gate 7 consists of an AND gate A3 which is energized when ordinary data is being translated to RLL coded data, and AND gate A4 is energized when RLL coded data is being converted to ordinary data. Clocking pulses are applied to the translator to operate the various gates and shift registers.

The operation of the translator shown in Fig. 1 will be described with the aid of Fig. 2, which shows the contents of read-only memory 1. The upper sixteen memory locations are use...