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# Binary Adder Using Josephson Devices

IP.com Disclosure Number: IPCOM000082234D
Original Publication Date: 1974-Oct-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 45K

IBM

## Related People

Herrell, DJ: AUTHOR [+2]

## Abstract

A binary adder using parallel and antiparallel inputs together with Josephson tunneling devices can be realized from simple logic blocks. In Fig. 1, the Josephson device is indicated by the block labeled J while three control lines having current inputs A, B, C are associated therewith. The directions of each input current A, B, and C can be either parallel or antiparallel to the Josephson gate current I(g). The term "parallel" as used herein means parallel and in the same direction as the gate current, while the term "antiparallel" means parallel and in the opposite direction to the gate current.

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Binary Adder Using Josephson Devices

A binary adder using parallel and antiparallel inputs together with Josephson tunneling devices can be realized from simple logic blocks. In Fig. 1, the Josephson device is indicated by the block labeled J while three control lines having current inputs A, B, C are associated therewith. The directions of each input current A, B, and C can be either parallel or antiparallel to the Josephson gate current I(g). The term "parallel" as used herein means parallel and in the same direction as the gate current, while the term "antiparallel" means parallel and in the opposite direction to the gate current.

A gain curve for the Josephson device J of Fig. 1 is shown in Fig. 2. This is a plot of the maximum Josephson current I(m) through the device, as a function of the total control current I(c) (which is the net current achieved by the combination of A, B, and C). For instance, if all control currents A, B, and C are in the same direction, a control current magnitude of plus or minus 3I will be achieved. In this plot, antiparallel control currents are denoted by negative polarity, while parallel control currents are denoted by positive polarity.

The asymmetric gain curve of Fig. 2 allows multiple functions to be performed by device J. For instance, with a bias current I(g) as shown, only one parallel input is required to switch the device to its voltage state, while three antiparallel currents are required to switch it to its voltage state using the left-hand portion of the gain curve.

In the circuit operations to be described, it should be understood that the antiparallel inputs are applied before application of the parallel inputs, due to the latching characteristics of Josephson devices. That is, if a parallel input is applied before the antiparallel inputs, the device will remain in its voltage state even though antiparallel inputs are later to be provided, thereby removing selectivity of voltage state in accordance with the total combination of the inputs A, B, C.

For a three-input gate device, the following possible combinations exist. Inputs (A,B,C) Function PPP (all parallel) A+B+C AAA (all antiparallel) ABC PPA (mixed) (A+B)C+AB AAP (mixed) A(B+C).

The mixed gate provides a useful tool in the implementation of an adder.

Fig. 3 shows a single stage of a parallel binary adder, which...