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Memory Cell Sensing Scheme

IP.com Disclosure Number: IPCOM000082255D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Anderson, KL: AUTHOR [+2]

Abstract

A four-device memory cell 10 is coupled to precharged bit lines 12 and 14 having a higher bias than the normal sense amplifier bias on pads 16 and 18. The higher voltage on bit lines 12 and 14, and thus at the corresponding cell nodes A and B, allows longer periods between refresh intervals for cell 10, reducing cell power for a given cell leakage.

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Memory Cell Sensing Scheme

A four-device memory cell 10 is coupled to precharged bit lines 12 and 14 having a higher bias than the normal sense amplifier bias on pads 16 and 18. The higher voltage on bit lines 12 and 14, and thus at the corresponding cell nodes A and B, allows longer periods between refresh intervals for cell 10, reducing cell power for a given cell leakage.

The higher bias on bit lines 12 and 14 is provided without disturbing the bias at the sense amplifier, not shown, which is coupled to pads 16 and 18, by isolating the bit lines 12 and 14 from pads 16 and 18, respectively, with diodes T1 and T2 having respective capacitors C1 and C2 connected across the diodes.

In operation, bit lines 12 and 14 are precharged to, say, 6 volts by source VH when a restore pulse is applied to line R and transistors T3 and T4 are turned on. Since the diodes T1 and T2 and capacitors C1 and C2 are located between pads 16 and 18 and source VH, the bias on pads 16 and 18 remains at its normal value of, say, 3.1 volts.

The voltage on bit lines 12 and 14 is transferred, as desired, to nodes A and B through transistors T5 and T6, controlled by the word line, and thus to storage transistors T7 and T8, to maintain stored information in cell 10 for a longer period of time without refreshing than could be realized if the bit line voltage was at the lower sense amplifier bias of 3.1 volts.

When the cell is read, transistors T3 and T4 are off and transistors T5 and T6 are on....