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Bit Manipulator

IP.com Disclosure Number: IPCOM000082259D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Hanna, CA: AUTHOR [+2]

Abstract

Bit manipulator 10, Fig. 1 is a high-speed device that selects certain bits from two input WORDS 1, 2 of N bits each (e.g., N = 32), and assembles the selected bits so that they appear in a specified order as an OUTPUT word of, for example, N bits.

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Bit Manipulator

Bit manipulator 10, Fig. 1 is a high-speed device that selects certain bits from two input WORDS 1, 2 of N bits each (e.g., N = 32), and assembles the selected bits so that they appear in a specified order as an OUTPUT word of, for example, N bits.

Buffers 11, 12, respectively, reduce input loading to the array 13 by storing the bits of WORDS 1, 2, respectively. The outputs of buffers 11, 12 are fed to a 2N-input multiplexer array 13 which has a number of identical stages equal to the number, e.g., N, of bits chosen for the OUTPUT word.

Cache memory 14 stores CACHE DATA that act as controls for array 13 for often-used functions to be performed on the data bits of WORDS 1, 2. Memory 14 is addressed by the address input CACHE ADDRESS & CONTROLS. By way of example, if memory 14 is a sixty-four word memory, a six-bit cache address can readily be used to select one of these often-used functions, and the output of memory 14 has N x 8 bit positions.

Each stage, cf. Fig. 2, of array 13, has eight identical parallel multiplexers 15-22, each of which has eight inputs. The outputs of multiplexers 15-22 are fed to the input of another eight-input multiplexer 23. Multiplexers 15-22 are controlled by the first three bits of an eight-bit word selected from memory 14, and multiplexer 23 is controlled by the next three bits and the "0" SELECT bit which is the seventh bit of the memory word being provided. An exclusive OR gate 24 exclusively OR's the output of mult...