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Monolithic Studs for Interlevel Connectors

IP.com Disclosure Number: IPCOM000082275D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 84K

Publishing Venue

IBM

Related People

Platter, V: AUTHOR [+2]

Abstract

In any multilevel semiconductor device structure, the resistance between levels must be as low as possible. If the topography which is introduced by the usual via hole through the interlevel insulation must be eliminated, metal "studs" or "risers" must be formed to connect the levels; then a planarizing insulator is deposited and etched to expose the surface of the studs.

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Monolithic Studs for Interlevel Connectors

In any multilevel semiconductor device structure, the resistance between levels must be as low as possible. If the topography which is introduced by the usual via hole through the interlevel insulation must be eliminated, metal "studs" or "risers" must be formed to connect the levels; then a planarizing insulator is deposited and etched to expose the surface of the studs.

The lowest via resistance is obtained if both the interconnection metallurgy (wiring pattern on a given level) and the interlevel studs are formed from a single layer of metal.

Such a monolithic metallurgy structure can be fabricated using anodic processing. In this process, the starting structure is a semiconductor substrate with the appropriate diffusion and isolation regions, and an overlying passivating layer with the necessary openings to the substrate. On the surface of the substrate, the composite film shown in Fig. 1 is depicted. The very thin (100-150 angstrom) underlay metal 10 is one which can be converted to an insulating layer, under conditions compatible with device processing; a typical underlay metal would be hafnium. Metal 11 is an aluminum-copper or aluminum-copper- silicon alloy and layer 12 is pure aluminum.

As shown in Fig. 2, a thin porous oxide layer 13 is produced on the surface of layer 12 by anodization in oxalic acid and serves as a base for the subsequent photoresist layer 14. As shown in Fig. 3, an opening 18 is made in layer 14 over the location of the desired stud.

A barrier layer 15 is formed by anodization in ammonium borate in ethylene glycol to about 75 volts...